The present document is based on Japanese priority documents JP 2001-214904, filed in the Japanese patent office on Jul. 16, 2001, the entire contents of which being incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory and a method of manufacturing the same, and more particularly relates to a dynamic random access memory that is a semiconductor memory with capacitors and a method of manufacturing the same.
2. Description of Related Art
A dynamic random access memory (hereafter, referred to as DRAM) of a semiconductor memory is provided with single cell transistor 211 and single capacitor 221, as shown in FIG. 11A. A gate of the cell transistor 211 is connected to a word line 231. Further, one diffusion layer of the cell transistor is connected to a bit line 241, and the other diffusion layer of the cell transistor 211 is connected to one electrode of the capacitor 221. Furthermore, the other electrode of the capacitor is connected to a plate electrode.
A memory cell of single-transistor-single-capacitor type having the above mentioned configuration is widely used since it has an advantage over other memory devices in achieving a higher degree of integration. However, there is always demands for even higher degree of integration in DRAM. Enormous efforts have been tried to advance miniaturization of such memory cells.
As a typical DRAM cell, a stack type capacitor cell and a trench type capacitor cell have been put to practical use until now. However, in order to form the memory cells of these types, it is inevitable that their structures become more complex if further reduction of cell area is attempted.
The DRAM memory comprises: a capacitor for accumulating memory charge, a transistor for receiving and outputting the charge, a bit line that is connected to the transistor for writing and reading data, and a word line to control on/off switch action of the transistor. In the DRAM memory cell, major development effort has been spent on how to reduce its cell size.
The reduction of the cell size while maintaining a required amount of the charge to be accumulated in the capacitor of the cell is one of most important issues of the development. Instead of a memory cell in which a capacitor is formed in a flat layout referred to as a planer type, the above mentioned cell structures such as the trench type, the stack type or the like are employed to make the capacitor structure three-dimensional in order to increasing the amount of charging capacitance within a smaller area size. Furthermore, as a material having a higher dielectric constant, for example, tantalum oxide (Ta2O5) and the like are used as an insulation film of the capacitor.
It is popular to use memory cells configured with a folded bit line system as shown in FIG. 11B. Such memory cells have been known to share a higher noise resistance characteristic found in conventional cell read-out operation. However, it is also known that the minimum memory cell area can not be less than 8F2 in such memory cell if the minimum machining dimension is assumed to be F. In order to attain less memory cell size, it is desirable to employ a layout configuration referred to as an open bit line system. FIGS. 11B, 11C show connection diagrams of the memory cells having configurations of the folded bit line system and the open bit line system, respectively.
As shown in FIG. 11, in memory cells with the folded bit line system, memory cells 201, each of which comprises the cell transistor 211 and the capacitor 221, are arranged so as to be connected to every other line of the word lines 231 between the bit lines 241. Further, the memory cells 201 are arranged so as to be connected to every other line of the bit lines 241 between word lines 231.
As shown in FIG. 11C, in memory cells with the open bit line system, the memory cell comprises the cell transistor 211 and the capacitor 221 and arranged so as to be connected to each word line 231 between the bit lines 241.
However, in view of improving the degree of integration in the DRAM, a more complex structure may have to be employed in order to form the memory cell of the stack type capacitor cell or the trench type capacitor cell if further miniaturization of the memory cell and further reduction of the cell area are tried.
There is constant demand for further reduction of the memory cell size. It is desirable to provide a memory cell that can be manufactured with simpler and easier process while securing cell charge of about 30 fC (femto-coulomb) that is required to maintain storage of data in the memory.
According to the present invention, a semiconductor memory apparatus is provided to solve or alleviate the above-mentioned problems.
The semiconductor memory according to an embodiment of the present invention comprises a dynamic random access memory. A memory cell of the dynamic random access memory comprises: a semiconductor pillar; a capacitor in which one side of the semiconductor pillar is used as the capacitor""s electrode; and a longitudinal insulated gate static induction transistor in which the other side of the semiconductor pillar is used as an active region of the transistor. Furthermore, a bit line is connected to the semiconductor pillar.
In the semiconductor memory, the capacitor for accumulating charge, the insulated gate static induction transistor and the bit line are configured so that they are piled up in a longitudinal direction. Separations between the respective memory cells are realized with a plate electrode of the capacitor embedded in a groove. Accordingly, a smaller average plane area occupied by the memory cell may be achieved.
Furthermore, in the memory cell, the longitudinal insulated gate static induction transistor is used as a word transistor of the memory cell. Accordingly, even if gate length of the transistor is made longer, it does not cause increasing of a cell area size. It is possible to accommodate sufficient margin in the gate length of the transistor. Furthermore, an amount of charge accumulated in the capacitor may be increased by extending length of the charge accumulation portion to a depth direction. Accordingly, the required capacitance may be secured without having any severe limitation even if the miniaturization is advanced further.
According to another embodiment of the present invention, a method of manufacturing a semiconductor memory is provided. Such method includes forming of a substrate by forming three layers one by one. The three layers are, from the bottom side, a semiconductor substrate of a first conductive type, a first semiconductor layer of a second conductive type, and a second semiconductor layer of a second conductive type having a lower concentration than that of the first semiconductor layer.
The method further includes forming of a groove, which is trenched in the semiconductor substrate, on a predetermined region of the substrate, and forming of a semiconductor pillar in form of a pillar, which is mainly composed of the first semiconductor layer and the second semiconductor layer, between the grooves.
The method further includes forming of a plate electrode of a capacitor by embedding conductor (electrical conducting material) via the semiconductor substrate, the first semiconductor layer and a capacitor insulation film in the groove, in such a way that the conductor faces the first semiconductor layer within the groove.
The method further includes forming of a word line, which includes a gate electrode of an insulated gate static induction transistor, by embedding conductor via the plate electrode, the first semiconductor layer, the second semiconductor layer and an insulation film, The conductor is configured in such a way that the formed conductor body faces the second semiconductor layer on the plate electrode.
The method further includes forming of a drain region of the insulated gate static induction transistor composed of a second conductive type semiconductor region of a higher concentration than that of the second semiconductor layer on a top surface of the semiconductor pillar.
The method further includes forming of an interlayer insulation film on the substrate, and then forming a bit line of a memory cell array connected to the drain region, on the interlayer insulation film.
According to the method of manufacturing the semiconductor memory, the capacitor for accumulating charge, the insulated gate static induction transistor and the bit line are formed in the structure in which they are longitudinally piled up, and the separation between the respective memory cells are realized with the plate electrode of the capacitor embedded in the groove. Accordingly, a smaller average plane area occupied by the memory cell may be achieved.
In the present embodiment, the conductor is embedded via the thin insulation film so as to form the plate electrode after the formation of the groove, and the conductor is embedded via the insulation film so as to form the word line. Accordingly, the process is made easier. Furthermore, formation of a fine contact within the memory cell is done only by forming a bit contact to connect the bit line. Accordingly, the process is simplified and load is decreased.
Furthermore, the gate length of the longitudinal insulated gate static induction transistor is directed to the depth direction. Accordingly, it does not cause increasing of a cell area size even if the gate length of the transistor is made longer. Furthermore, it is possible to form the transistor of the gate length with sufficient margin. Furthermore, the charges capacitance accumulated in the capacitance may be made greater by increasing the length of the charge accumulation portion to the depth direction. Accordingly, the capacitor with a large capacitance may be formed without any severe limitation on the occupied surface area even if the miniaturization is further advanced. That is, the capacitor with a sufficient amount of the capacitance may be formed.